Track 7 / Module 7.2
High-Throughput DMA Communication Engines
UART IDLE-line plus DMA for variable-length frames, ping-pong buffers on HT/TC, and cache maintenance on Cortex-M7.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Get it
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.