What never made it into the datasheet
Be the engineer who knows why it failed.
When the team is stuck on a bus that hangs after reset, a fault that points nowhere or jitter nobody can explain, one person finds the cause. That is the lost art of embedded development, written down as handbooks so you can be that person.
- Tracks
- 10
- Modules
- 53
- Per track
- ₹4,999$99
Firmware has no margin for error. One wrong bit is all it takes.
Why fundamentals matter
Skip the fundamentals and both the company and the engineer pay for it.
This knowledge was passed from senior engineer to junior, one board bring-up at a time. Those engineers are retiring or moving on, vendor HALs hide the registers, and code generators write firmware without ever looking at the hardware. Fewer engineers can do this every year, and the ones who still read the reference manual and the errata are the ones teams escalate to. That is your opening.
For the organisation
- Bugs found late become board respins, slipped launches and units that come back from the field.
- The hard faults all land on the same few senior engineers, who are pulled off the roadmap to chase them.
- Returns get closed as “can’t reproduce”, and the same failure ships again.
For the engineer
- You’re stuck on a fault that points nowhere, with no way to narrow it down.
- You can’t defend a design decision in review, because you can’t say which register or timing proves it.
- You stay the one waiting for an answer, instead of the one the team turns to for it.
Where it fails quietly
-
Polls a hardware status register in a tight loop
The register isn’t declared
volatile. At optimisation levels like-O2the compiler reads it once into a core register, and the loop never exits. -
Calls an RTOS kernel API from an interrupt handler
The interrupt’s priority is above the highest level the kernel allows for API calls. With the kernel’s checks switched off, it passes the bench, then corrupts scheduler state under load in the field.
-
Initialises a peripheral by writing its registers
Its clock isn’t enabled yet. Depending on the part, the write is ignored or raises a bus fault, which may be reported imprecisely, so the saved return address points at unrelated code.
The fundamentals are the difference.
Embedded Institute writes that craft down. Each module takes one real problem, a write buffer that reports a fault three instructions late or an I2C slave holding SDA low after a reset, from symptom to root cause to a fix that holds in production. Handbooks you keep open at the bench, and the depth you bring into the design review.
If you can read a register map, trace a bus fault and inspect the assembly, you can tell a working driver from a latent field failure, whoever or whatever wrote it. The handbooks teach the physics and architecture underneath, so you know what to ask, what to check and when something is wrong.
The curriculum
10 tracks, 53 modules, written in order. Each track shows its tentative release quarter. Select any module to see its path and how to get it.
Writing now · Tentative Q4 2026
The Compiler, Linker & Boot Architecture
How source becomes flash bits and boots the silicon: toolchain stages, file formats, optimisation, the ABI, linker scripts and the traps that only appear at -O2.
Typical cost of one failure$8,000–$12,000 in senior triage (80–120 hours chasing Heisenbugs), or $25,000+ in microcontroller upgrades over a production run. Why this cost
Planned · Tentative Q4 2026
Deep C, Determinism & Pragmatic Standards (MISRA / CERT C)
The C failure modes that MISRA C and CERT C exist to tame, and an engineering-first way to apply both without drowning in warnings.
Typical cost of one failureAbout $15,000 in developer time lost to alert fatigue over a project. Why this cost
Planned · Tentative Q1 2027
The Hardware-Software Interface (HSI)
What the silicon does before and around your code: reset pin states, clock trees, register access, interrupt controllers and DMA.
Typical cost of one failure$3,000–$8,000 in burned prototype assemblies, plus about $7,500 of oscilloscope time hunting startup HardFaults. Why this cost
Planned · Tentative Q1 2027
Architecture, State Machines & Concurrency
Designing firmware that stays deterministic as it grows: API ergonomics, state machines, event loops, lock-free queues and memory budgets set before part selection.
Typical cost of one failure$15,000–$25,000 for an emergency hardware re-spin, and about $20,000 of engineering time lost debugging deadlocks. Why this cost
Planned · Tentative Q2 2027
Defensive Engineering & Crash Forensics
Supervision, fault containment and post-mortem analysis: watchdogs, brownout, the MPU, HardFault handlers and reading a dead unit's RAM.
Typical cost of one failure$40,000+ in warranty replacements (for example 500 bricked units at $80 each), or inventory written off as unreproducible. Why this cost
Planned · Tentative Q2 2027
Verification, Silicon Stress Testing & Embedded CI/CD
Testing firmware on the host, in emulation and on real hardware, stressing it at the corners, and gating every commit in CI.
Typical cost of one failure$30,000–$100,000 for an emergency field firmware update, and about $35,000 on test equipment you may not need. Why this cost
Planned · Tentative Q3 2027
Communication Protocols, Packet Framing & Bus Interfacing
Keeping buses alive and data intact: lockup recovery, DMA receive engines, binary framing, streaming parsers and CRCs.
Typical cost of one failure$10,000–$50,000 in service dispatches or penalty fees, and up to $50,000+ in unnecessary processor upgrades. Why this cost
Planned · Tentative Q3 2027
Design for Manufacturing (DFM) & Production Engineering
Firmware for the factory line: test points, factory test modes, fast flashing, second-source silicon and locking debug ports safely.
Typical cost of one failure$20,000–$35,000 in operator labour on a 100k-unit run, and $50,000–$250,000+ if a line stops during a shortage. Why this cost
Planned · Tentative Q4 2027
The Software Supply Chain: COTS, Packages & Bootloaders
Shared code across products, dependency updates, build traceability, open-source licences and bootloaders that don't brick a unit.
Typical cost of one failure$30,000–$60,000 in emergency legal review and driver rewrites, and $80,000+ in field replacements after a failed bootloader hand-off. Why this cost
Planned · Tentative Q4 2027
The Lost Art of Embedded Project Management
Running firmware projects against physical reality: hardware phase gates, lab and tooling lead times, cross-team communication, dashboards and field returns.
Typical cost of one failure$100,000–$300,000+ in lost early-to-market revenue on a commercial product, and about $45,000 in scrapped mould tooling. Why this cost
AI Embedded Developer Toolkit · The add-on for your daily workflow
AI writes the first draft. You sign the work.
You’re already pasting datasheets and headers into an assistant. The AI Embedded Developer Toolkit gives that habit structure, with prompts and scripts for the slow parts of bench work, so you spend your hours on judgement instead of retyping register tables. The tracks give you the fundamentals to know when the answer is wrong.
Toolkit₹12,499$249
₹7,499$149 if you bought a track or the all-tracks plan. Included in All-Access.
- Datasheet extractionScripts that pull register bitfields out of datasheet PDFs into C structs.
- Test vectors and mocksPrompts and generators that draft unit test vectors and mocks from your C headers.
- First-pass reviewPrompts for a first review of driver code, before a human one.
Everything the toolkit produces is a draft: you check it against the reference manual, and the judgement stays with you. That’s what the tracks are for. Included in All-Access and in the Site and Enterprise licences.
Pricing
Prices are in US dollars.Prices are in Indian rupees. An investment in the skill your next step rests on. Every purchase comes with a GST/VAT invoice your company can reimburse.
All tracks are training and learning material. You’re responsible for evaluating your own system’s specifications and applying the appropriate measures. Training notice
Track
₹4,999$99
Every module in a track as a searchable PDF handbook.
Pre-order ₹3,499$69
30% off any track that’s still being written. Each module is delivered the day it’s released; the price returns to ₹4,999$99 once every module is out.
Modules are sold only as part of a track. There are no single-module purchases.
All 10 tracks
₹29,999$599 ₹49,990$990
The whole curriculum in one purchase. Tracks still being written are delivered the day they’re released, through Q4 2027.
All-Access
₹34,999$699 ₹62,489$1,239
All 10 tracks plus the AI Embedded Developer Toolkit, in one purchase.
Already bought a track? Upgrade with credit
Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Enter the email you bought with and we’ll send a checkout link for the all-tracks plan at the difference.
Small Team
$1,799
Up to 10 engineers. One project team.
- All 10 tracks as PDF, plus Markdown/HTML for your internal wiki (Confluence, Notion)
- A signed one-page grant of internal distribution
Site / Department
$2,900
Up to 50 engineers. One facility or division.
- Everything in Small Team
- The code and extra files that ship with the modules
- The AI Embedded Developer Toolkit for the whole team
Global Enterprise
from $8,900
Unlimited engineers. Worldwide, every site.
- Everything in Site / Department
- Unrestricted internal distribution across all sites
Critical failures, root-cause analyses, and quarterly curriculum drops.
Deep dives into real embedded failures, traced from symptom to cause, plus first notice when new modules open for enrollment.
Every email has an unsubscribe link.
Track 1 / Module 1.1
The Bare-Metal Genesis: Tools, File Formats & Startup
The four toolchain stages, ELF, Intel HEX and Motorola S-record formats, and the crt0 path from the vector table and Reset_Handler to main().
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.2
Aggressive Optimizations & Link-Time Elimination
What -O0 to -Oz actually change, section-level dead-stripping with --gc-sections, and LTO without losing your ISRs.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.3
The ABI, Stack Frames & Polyglot Runtime
AAPCS argument and callee-saved registers, prologues and 8-byte stack alignment, and calling between C, C++ and assembly.
- Status
- Writing now
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.4
Stack Architecture, Slot Merging & Frame Diagnostics
How compilers share stack slots across scopes, what stops them, and measuring worst-case depth with -fstack-usage.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.5
Advanced Memory Surgery: Linker Scripts & MAP Forensics
Custom sections, LMA/VMA splits, functions run from RAM, alignment for caches and DMA, and reading the .map file.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.6
The Embedded C Library: Specs, Syscalls & Bloat Traps
Newlib, newlib-nano and picolibc, retargeting _write() and _sbrk(), and why one printf() can pull in tens of kilobytes.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 1 / Module 1.7
The Hall of Death Traps & The Day 0 Contract
volatile, strict aliasing, barriers and undefined behaviour that pass at -O0 and fail at -O2, and why the optimisation level is fixed on day 0.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 1, ₹4,999$99
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
This module is part of Track 1 and isn’t out yet. Buy the track and you get it the day it ships.
All 7 modules in one purchase. Modules not yet released are delivered the day they ship. Everything you spend on individual tracks within 12 months of your first track purchase is credited 100% toward the all-tracks plan. Company licences cover the whole library for your team, from $1,799, on invoice (USD). Need your company to pay? Letter for your boss.
Track 2 / Module 2.1
The Fractured Foundation: C's Dark Corners & Undefined Behavior
Integer promotion, signed shifts, pointer arithmetic, type punning and sequence points on 16-bit and 32-bit targets.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 2
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 2 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2026.
Track 2 / Module 2.2
Safety vs. Security: Pragmatic MISRA C & CERT C
The few rules that prevent most runtime failures, the ones that hurt driver code, and how to document a deviation for a register access or a naked ISR.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 2
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 2 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2026.
Track 2 / Module 2.3
Static Analysis Engines & The Developer Friction Tax
Linters versus path-sensitive analysers, alert fatigue, baselining legacy code and keeping CI fast.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 2
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 2 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2026.
Track 2 / Module 2.4
The Critical Guardrails: Bounding Types, Memory & Control Flow
Fixed-width types, explicit casts, static pools instead of malloc, bounded recursion and exhaustive switch statements.
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 2
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 2 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2026.
Track 2 / Module 2.5
Dynamic Analysis, Sanitizers & Runtime Bounds Checking
UBSan on target, ASan under QEMU, and an assert() that logs to non-volatile memory instead of hanging in while(1).
- Status
- Planned
- Track release
- Q4 2026 (tentative)
- Included in
- Track 2
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 2 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2026.
Track 3 / Module 3.1
The Silicon Wake-up: High-Z States & Pre-Execution Hardware Reality
Floating pins during power ramp and reset, what they switch on downstream, and setting critical GPIOs in the first lines of Reset_Handler.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 3 / Module 3.2
The Modern Clock Labyrinth: Oscillators, PLLs & Latency Ramps
Crystal load capacitance and cold-start stalls, the VCORE, Flash wait-state and PLL sequence, and clock security fallback.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 3 / Module 3.3
Memory-Mapped I/O, Atomic Access & Bit-Banding
Read-modify-write hazards, set/clear registers and bit-banding, AHB/APB wait-states, and errata workarounds at register level.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 3 / Module 3.4
Interrupt Controllers (NVIC/PLIC), Latency & Preemption Math
Priority grouping, tail-chaining and late arrival, PRIMASK versus BASEPRI, and keeping nested interrupts within the main stack.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 3 / Module 3.5
High-Speed DMA Controllers & Cache Coherency
Streams, FIFOs and circular mode, HT/TC handoffs, and cleaning and invalidating D-cache around DMA buffers on Cortex-M7.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 4 / Module 4.1
Architectural Ergonomics: Complex to Author vs. Complex to Consume
Where to put the complexity: ownership transfer, opaque handles and reentrant APIs that are hard to misuse.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 4
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 4 / Module 4.2
Deterministic State Machines: FSMs & HSMs
Super-loop, cooperative and RTOS trade-offs, flat and hierarchical state machines, entry/exit actions and event queues.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 4
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 4 / Module 4.3
Breaking System-Level Recursion & Reentrancy Traps
Event cascades that loop back into the driver, why call-tree analysis misses them, and one-way data flow that prevents them.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 4
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 4 / Module 4.4
Concurrency Primitives & Lock-Free Data Structures
Races, deadlocks and priority inversion, inheritance versus ceiling protocols, and SPSC ring buffers shared with ISRs.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 4
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 4 / Module 4.5
Silicon Sizing: The Deterministic RAM/ROM Estimator
Estimating Flash and RAM budgets before part selection, including SDK and RTOS overhead, OTA banks, DMA buffers and margins.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 4
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.
Track 5 / Module 5.1
Hardware Supervision: Internal vs. External Windowed Watchdogs
Why a watchdog kicked from a timer ISR keeps a frozen device alive, windowed watchdogs, and multi-task liveness checks.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 5 / Module 5.2
The Dying Gasp: Power-Good, Brownout & Emergency State Persistence
PGOOD versus BOR/PVD, sizing hold-up capacitance, and the shutdown ISR that saves state before the rail collapses.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 5 / Module 5.3
Memory Protection Units (MPU) & Fault Containment
MPU regions without an RTOS, trapping null pointers at 0x00000000, no-execute RAM and stack guard regions.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 5 / Module 5.4
Custom HardFault Handlers & Crashdump Recorders
Extracting the stacked PC, LR and xPSR, decoding CFSR, HFSR, MMFAR and BFAR, and saving a crash record that survives reset.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 5 / Module 5.5
Production Forensics: RAM Dumping & MAP-File Reconstruction
Pulling SRAM over a bootloader or UART when SWD is fused off, then rebuilding variables, TCBs and call stacks from the .map and .elf.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 5 / Module 5.6
The Production Diagnostics Paradox (Selective Debugging)
Dormant diagnostics in production builds, challenge-response unlock over CAN, UART or USB, and black-box logs triggered by faults.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 5
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 5 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 6 / Module 6.1
Host-Based Testing & Decoupled Mocking
Unity, CMock and FFF on the host, mocking at the HAL instead of raw registers, and host-versus-target differences.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 6
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 6 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 6 / Module 6.2
The $200 Pragmatic Hardware-in-the-Loop (HIL) Rig
A Raspberry Pi, relays and a programmable supply that power-cycle the board, flash it over SWD and drive the UART on every commit.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 6
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 6 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 6 / Module 6.3
Virtual Target Emulation (QEMU & Renode)
Headless Cortex-M and RISC-V emulation, multi-node boards with simulated peripherals, and regression runs in CI.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 6
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 6 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 6 / Module 6.4
Silicon Stress Testing & Corner Torture
Flooding CAN, I2C and SPI past rated load, temperature and voltage corners, and soak tests that expose leaks and the 49.7-day tick rollover.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 6
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 6 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 6 / Module 6.5
Headless Embedded CI/CD Automation
Containerised toolchains, zero-warning and static analysis gates, and failing builds that exceed their Flash or RAM budget.
- Status
- Planned
- Track release
- Q2 2027 (tentative)
- Included in
- Track 6
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 6 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q2 2027.
Track 7 / Module 7.1
The Autopsy of Bus Failures: Hardware Hangs & Recovery
I2C stuck-low and the 9-clock SCL recovery, CAN bus-off, UART FE/ORE/NE errors and SPI CPOL/CPHA mismatches.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 7 / Module 7.2
High-Throughput DMA Communication Engines
UART IDLE-line plus DMA for variable-length frames, ping-pong buffers on HT/TC, and cache maintenance on Cortex-M7.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 7 / Module 7.3
Binary Framing Architectures: Escaping the ASCII/JSON Trap
Delimiter versus length-prefix framing, COBS, SLIP and HDLC, and endian-neutral serialisation.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 7 / Module 7.4
Asynchronous Streaming Parsers: The Non-Blocking FSM
A byte-by-byte parser that survives dropped and corrupted bytes and resynchronises without losing the next frame.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 7 / Module 7.5
Wire-Speed Integrity: CRC Engines & Checksums
Why 8-bit checksums miss burst errors, choosing CRC-8, CRC-16-CCITT or CRC-32, lookup tables and hardware CRC units.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 7
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 7 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 8 / Module 8.1
Test Points & Bed-of-Nails Fixture Design
Test point size, spacing and placement, pogo pin wear, and the contact problems behind false line failures.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 8
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 8 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 8 / Module 8.2
Factory Test Firmware (ICT / FCT Modes)
One production binary with a built-in test mode, unlocked by handshake or strap pin, plus in-fixture ADC and crystal calibration.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 8
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 8 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 8 / Module 8.3
Flash Cycle-Time Optimization & Gang Programming
Cutting SWD programming time per board, and multiplexed and gang programming for panels.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 8
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 8 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 8 / Module 8.4
Shortage-Ready Architecture & Drop-in Chip Replacements
Detecting the part at boot from device ID, revision or straps, one abstraction for alternates, and multi-target Kconfig/CMake builds.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 8
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 8 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 8 / Module 8.5
Factory Silicon Lock-down & Debug Security
Pre-programmed parts versus fixture flashing versus staged bootloaders, and locking debug (e.g. STM32 RDP Level 2) only after verified flash.
- Status
- Planned
- Track release
- Q3 2027 (tentative)
- Included in
- Track 8
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 8 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q3 2027.
Track 9 / Module 9.1
Code Reuse Architectures: Monorepo vs. Polyrepo
Submodule pain, one repository for all targets, atomic cross-product commits, and when each model wins.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 9
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 9 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 9 / Module 9.2
Dependency Propagation: Pushing Upstream Fixes
Stopping silent divergence with automated update pull requests, semantic versioning for ABI changes and regression gates.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 9
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 9 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 9 / Module 9.3
Forensic Traceability: Immutable Build Stamping
Embedding the Git SHA, dirty flag and toolchain version in .rodata, and pairing it with the chip UID and board revision.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 9
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 9 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 9 / Module 9.4
Open-Source Governance, FOSS Licensing & SCA
Composition scanning in CI, what static linking means under GPLv3 versus MIT, BSD, Apache and LGPL, and CVE triage for non-networked devices.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 9
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 9 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 9 / Module 9.5
Bootloader Architecture & Secure Firmware Updates
CRC versus SHA-256 versus Ed25519/ECDSA, dual-bank layouts, golden images, anti-rollback, and a clean jump to the application.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 9
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 9 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 10 / Module 10.1
The Silicon-Anchored Lifecycle: Beyond Pure Agile
Firmware sprints inside EVT, DVT and PVT gates, the DVT feature freeze, and a triage matrix for late scope.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 10
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 10 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 10 / Module 10.2
The Physical Dependency Gantt: Scheduling Labs, Tooling & Vendors
Planning around test-lab queues, mould and PCB lead times and reliability testing, with buffers for errata and bring-up.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 10
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 10 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 10 / Module 10.3
Cross-Functional Diplomacy: Hardware, Firmware & Executive Alignment
Settling hardware-or-firmware disputes with scope traces and register dumps, HSI sign-off before board release, and bad news delivered early.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 10
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 10 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 10 / Module 10.4
Operational Telemetry: Dashboards for Developers, Managers & Leadership
Three tiers of readiness data: per-commit memory and CI health, defect arrival versus closure, and phase-gate go/no-go.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 10
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 10 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
Track 10 / Module 10.5
The RMA & Field-Issue Triage Pipeline
From returned unit to backlog: reading build stamps and UIDs, retrieving the matching .elf and .map, and separating component, errata and firmware faults.
- Status
- Planned
- Track release
- Q4 2027 (tentative)
- Included in
- Track 10
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Track 10 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q4 2027.
I want Track 2 sooner
Deep C, Determinism & Pragmatic Standards (MISRA / CERT C). Tentative Q4 2026.
I want Track 6 sooner
Verification, Silicon Stress Testing & Embedded CI/CD. Tentative Q2 2027.
I want Track 7 sooner
Communication Protocols, Packet Framing & Bus Interfacing. Tentative Q3 2027.
I want Track 8 sooner
Design for Manufacturing (DFM) & Production Engineering. Tentative Q3 2027.
I want Track 9 sooner
The Software Supply Chain: COTS, Packages & Bootloaders. Tentative Q4 2027.