Track 3 / Module 3.5
High-Speed DMA Controllers & Cache Coherency
Streams, FIFOs and circular mode, HT/TC handoffs, and cleaning and invalidating D-cache around DMA buffers on Cortex-M7.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Get it
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.