Track 3 / Module 3.4
Interrupt Controllers (NVIC/PLIC), Latency & Preemption Math
Priority grouping, tail-chaining and late arrival, PRIMASK versus BASEPRI, and keeping nested interrupts within the main stack.
- Status
- Planned
- Track release
- Q1 2027 (tentative)
- Included in
- Track 3
Path
The step-by-step path for this module is published before it’s released.
Every module includesHandbook (PDF)
Some modules also ship extra files, such as code or register maps.
Get it
Track 3 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.