Track 4 / Module 4.4

Concurrency Primitives & Lock-Free Data Structures

Races, deadlocks and priority inversion, inheritance versus ceiling protocols, and SPSC ring buffers shared with ISRs.

Status

Planned

Track release

Q1 2027 (tentative)

Included in

Track 4

Path

The step-by-step path for this module is published before it’s released.

Every module includesHandbook (PDF)

Some modules also ship extra files, such as code or register maps.

Get it

Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.