Track 4 · Planned · Tentative Q1 2027

Architecture, State Machines & Concurrency

Designing firmware that stays deterministic as it grows: API ergonomics, state machines, event loops, lock-free queues and memory budgets set before part selection.

Track 4 isn’t on sale yet. It opens for pre-order when writing starts, with release planned for Q1 2027.

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Why each module matters

• 4.1Architectural Ergonomics: Complex to Author vs. Complex to ConsumeDecide where complexity belongs, so libraries written by senior engineers can be used safely by everyone else.
• 4.2Deterministic State Machines: FSMs & HSMsStructure a multi-task application as state machines in one stack, which can cut RAM use and remove a class of scheduling bugs.
• 4.3Breaking System-Level Recursion & Reentrancy TrapsFind the event loops that become recursion at system level, the crashes that appear only after days of running.
• 4.4Concurrency Primitives & Lock-Free Data StructuresShare data between ISRs and tasks with lock-free structures, instead of heavy mutexes that invite deadlock and starvation.
• 4.5Silicon Sizing: The Deterministic RAM/ROM EstimatorEstimate Flash and RAM before part selection, to reduce the risk of a mid-project respin for memory exhaustion.

The cost of a single failure

The failure it addresses

Undersized silicon forcing a late board re-spin, unrepeatable RTOS race conditions and system-level recursion.

Typical cost if it happens

$15,000–$25,000 for an emergency hardware re-spin, and about $20,000 of engineering time lost debugging deadlocks.

What the track teaches

Teaches upfront RAM and ROM sizing formulas, deterministic hierarchical state machines and lock-free hand-offs.

Cost benchmarks and engineering labour estimates are drawn from typical industry averages (fully loaded engineering rates of $80–$100 an hour, typical prototype fabrication costs, and low-to-mid volume manufacturing runs). They are provided for risk assessment, educational planning and internal budgeting only. No specific financial return, operational saving or outcome is guaranteed. All tracks